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Monday, 30 May 2011

VLSI Projects

  1. Design and Implementation of a Field Programmable CRC Circuit Architecture—IEEE 2009.
  2. Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency—IEEE 2009.
  3. Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits—IEEE 2009.
  4. Design of Network-on-Chip Architectures with a Genetic Algorithm-Based Technique—IEEE 2009.
  5. Efficient On-Chip Crosstalk Avoidance CODEC Design—IEEE 2009.
  6. Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits—IEEE 2009.
  7. Fault Secure Encoder and Decoder for Memory Applications—IEEE 2007.
  8. A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture—IEEE 2009.
  9. A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System—IEEE 2008.
  10. A Generalization of a Fast RNS Conversion for a New 4-Modulus Base—IEEE 2009.
  11. A VLSI Progressive Coding for Wavelet-based Image Compression—IEEE 2007.
  12. A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter—IEEE 2009.
  13. A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations—IEEE 2009.
  14. FPGA Implementation of Viterbi Decoder—IEEE 200
  15. Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic—IEEE 2008.
  16. A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture—IEEE 2009.
  17. Designing Efficient Online Testable Reversible Adders with New Reversible Gate—IEEE 2007.
  18. Deviation-Based LFSR Reseeding for Test-Data Compression—IEEE 2009.
  19. Hardware implementation of Variable Precision Multiplication on FPGA—IEEE 2009.
  20. Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension—IEEE 2009.
  21. Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST—IEEE 2009.
  22. Spread Spectrum Image Watermarking with Digital Design—IEEE 2009.

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