A novel dead-time elimination method is presented in this paper for voltage source inverters. This method is based on decomposing of a generic phase-leg into two basic switching cells, which are configured with a controllable switch in series with an uncontrollable diode. Therefore, dead-time is not needed. In comparison to using expensive current sensors, this method precisely determines the load current direction by detecting which anti-parallel diode conducts in a phase-leg. A low-cost diode-conduction detector is developed to measure the operating state of the anti-parallel diode. In comparison with complicated compensators, this method features simple logic and flexible implementation. This method significantly reduces the output distortion and regains the output RMS value. The principle of the proposed dead-time elimination method is described in detail. Simulation and experimental results are given to demonstrate the validity and features of this new method.
To avoid shoot-though in voltage source inverters (VSI), dead-time, a small interval during which both the upper and lower switches in a phase-leg are off, is introduced into the standard pulse width modulation (PWM) control of VSIs. However, such a blanking time can cause problems such as output waveform distortion and fundamental voltage loss in VSIs, especially when the output voltage is low.
To overcome dead-time effects, most solutions focus on dead-time compensation by introducing complicated PWM compensators and expensive current detection hardware. In practice, the dead-time varies with the gate drive path propagation delay, device characteristics and output current, as well as temperature, which makes the compensation less effective, especially at low output current, low frequency, and zero current crossing. Several switching strategies for PWM power converters have been proposed to minimize the dead-time effect. A dead-time minimization algorithm was also discussed earlier to improve the inverter output performance. A phase-leg configuration topology proposed prevented shoot through. However, an additional diode in series in the phase-leg increases complexity and causes more loss in the inverter. Also, this phase-leg configuration is not suitable for high-power inverters because the upper device gate turn-off voltage is reversely clamped by a diode turn on voltage. Such a low voltage, usually less than 2 V, is not enough to ensure that a device is in its off-state during the activation of its complement device.
High-power inverters usually need longer dead-time than those low-power counterparts. Also due to complicated structures and severe parasitic parameter variations, in practice, the dead-time for high-power inverters requires specific adjustment and/or compensation, and usually this process is time-consuming. For general applications, automatically eliminating dead-time by gate drive technology is a desired and complete solution. Gate drives with intelligent functions are in high demand due to the emerging technology of power electronics building blocks (PEBB) and intelligent power modules (IPM) because smart functions can improve power devices’ modularity, flexibility and reliability.
In this work, an effective dead-time elimination method is proposed. This method is based on decomposing of a generic phase-leg into two basic switching cells, which are configured with a controllable switch in series with an uncontrollable diode. Therefore, dead-time is not needed. In this paper, the effect of dead-time in VSIs will be first introduced. The principle of the proposed method to eliminate dead-time effect is explained in detail. Simulation and experimental results are provided to demonstrate the validity and features of the proposed novel method. Flexible implementation methods are also discussed.