The Tiger SHARC processor is the newest and most power member of this family which incorporates many mechanisms like SIMD, VLIW and short vector memory access in a single processor. This is the first time that all these techniques have been combined in a real time processor.
The TigerSHARC DSP is an ultra high-performance static superscalar architecture that is optimized for tele-communications infrastructure and other computationally demanding applications. This unique architecture combines elements of RISC, VLIW, and standard DSP processors to provide native support for 8, 16, and 32-bit fixed, as well as floating-point data types on a single chip.
Large on-chip memory, extremely high internal and external bandwidths and dual compute blocks provide the necessary capabilities to handle a vast array of computationally demanding, large signal processing tasks
As has been demonstrated in several application spaces, most notably the 3G telecoms infrastructure equipment market, TigerSHARC is the only DSP solution containing the performance and instruction set to enable an 'all software' approach. This means a TigerSHARC-based solution is better equipped to address manufacturer's requirements for flexibility, high-performance, reduced bill of materials cost and added capacity than traditional hardware approaches that rely heavily on ASICs (application-specific integrated circuits), FPGAs (field programmable gate arrays) and/or ASSPs (application specific standard products).
Through this combination, the TigerSHARC Processor gains the unique ability to process 1, 8, 16 and 32-bit fixed-point as well as floating-point data types on a single chip. This proprietary architecture establishes it in a leading position in the critical areas of performance, integration, flexibility and scalability. Optimising throughput, not just clock speed, drives a balanced DSP architecture and with throughput as the metric, the TigerSHARC Processor is the highest performance DSP for communications infrastructure and multiprocessing applications currently available.
While also providing high system performance it also retains the highest possible flexibility in software and hardware development - flexibility without compromise. For general purpose multiprocessing applications, TigerSHARC Processor's balanced architecture optimises system, cost, power and density.
A single TigerSHARC Processor, with its large on-chip memory, zero overhead DMA engine, large I/O throughput, and integrated multiprocessing support, has the necessary integration to be a complete node of a multiprocessing system. This enables a multiprocessor network exclusively made up of TigerSHARCs without any expensive and power consuming external memories or logic.
The latest members of the TigerSHARC family are the ADSP-TS201S, ADSP-TS202S and ADSP-TS203S. The ADSP-TS201S operates at 600 MHz with 24 Mbits and can execute 4,8 billion MACs per second while achieving high floating-point DSP performance. The ADSP-TS202S operates at 500 MHz with 12 Mbits and the ADSP-TS203S operates at 500 MHz with 4 Mbits.
The TigerSHARC Processor's parallelism capabilities allow for up to four 32-bit instructions per cycle while an enhanced communication instruction set reduces some of the mountainous signal processing functions associated with wireless down to a manageable level. The TigerSHARC also provides an unmatched level of both internal and external bandwidth that enable high computation rates and high data rate processing.
The combination of all the above mentioned features positions the TigerSHARC Processor as an excellent candidate for applications requiring extremely high throughput such as the channel decoding algorithms of wireless communications.