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Friday, 9 March 2012

The future of computers: 3D chip stacking

In a few weeks, Intel will release Ivy Bridge, the first mass-produced 22nm parts, and more importantly the first to use 3D “tri-gate” FinFET transistors. These CPUs will be incredibly fast and use very little power, but ultimately they are just another last-gasp effort to squeeze a little more life out of a material and process that will soon hit a wall. Computing is still predominantly single-threaded; throwing more transistors and more cores at a problem will only take you so far.

Fortunately, there’s another maturing technology that should provide a much-needed lease of life to the silicon industry: Chip stacking, or to give its formal name, 3D wafer-level chip packaging. Chip stacking is exactly what it sounds like: You take a completed computer chip (DRAM, say), and then place it on top of another chip (a CPU). As a result, two chips that used to be centimeters apart on a circuit board are now less than a millimeter apart. This reduces power consumption (transmitting data over copper wires is messy business), and also improves bandwidth by a huge amount.

Applied Materials machine in Singapore labObviously, though, you can’t just take a DRAM chip and whack it on top of a CPU. The chips need to be designed with chip stacking in mind, and it takes specialized machinery to actually line the dies up and attach them. To this end, Applied Materials — the company that makes all of the machines used by Intel, TSMC, Samsung, GloFo, and every other semiconductor manufacturer — and A*STAR’s Institute of Microelectronics (IME) have announced the opening of a bleeding-edge 3D chip packaging lab in Singapore. Built with a combined investment of over $100 million, the Centre of Excellence in Advanced Packaging features a 14,000 square foot cleanroom containing a complete 300-millimeter production line and 3D packaging tools that are unique to A*STAR. The Centre isn’t a commercial fab, however: It’s actually designed as a facility for other companies, such as TSMC or Samsung, to come and experiment with 3D packaging. As far as Applied Materials is concerned, of course, this is an excellent way to demonstrate and sell its machines.

Brain Gate

BrainGate is a brain implant system developed by the bio-tech company Cyberkinetics in 2003 in conjunction with the Department of Neuroscience at Brown University. The device was designed to help those who have lost control of their limbs, or other bodily functions, such as patients with amyotrophic lateral sclerosis (ALS) or spinal cord injury. The computer chip, which is implanted into the brain , monitors brain activity in the patient and converts the intention of the user into computer commands. Cyberkinetics describes that "such applications may include novel communications interfaces for motor impaired patients, as well as the monitoring and treatment of certain diseases which manifest themselves in patterns of brain activity, such as epilepsy and depression."

Currently the chip uses 100 hair-thin electrodes that sense the electro-magnetic signature of neurons firing in specific areas of the brain, for example, the area that controls arm movement. The activities are translated into electrically charged signals and are then sent and decoded using a program, which can move either a robotic arm or a computer cursor. According to the Cyberkinetics' website, three patients have been implanted with the BrainGate system. The company has confirmed that one patient ( Matt Nagle ) has a spinal cord injury, while another has advanced ALS.

BrainGate Neural Interface System

The BrainGate Neural Interface System is currently the subject of a pilot clinical trial being conducted under an Investigational Device Exemption (IDE) from the FDA. The system is designed to restore functionality for a limited, immobile group of severely motor-impaired individuals. It is expected that people using the BrainGate System will employ a personal computer as the gateway to a range of self-directed activities. These activities may extend beyond typical computer functions (e.g., communication) to include the control of objects in the environment such as a telephone, a television and lights.

The BrainGate System is based on Cyberkinetics' platform technology to sense, transmit, analyze and apply the language of neurons. The System consists of a sensor that is implanted on the motor cortex of the brain and a device that analyzes brain signals. The principle of operation behind the BrainGate System is that with intact brain function, brain signals are generated even though they are not sent to the arms, hands and legs. The signals are interpreted and translated into cursor movements, offering the user an alternate "BrainGate pathway" to control a computer with thought, just as individuals who have the ability to move their hands use a mouse

A Five-Level Zero Average Current Error Controlled Single-phase Grid-Interactive Inverter

For inverters, power quality is generally measured in terms of harmonic content and the magnitude of the ripple current. Current ripple for a conventional inverter is a function of inductor size, switching frequency and the number of discrete DC input levels (multi-level inverter). Zero average current error (ZACE) control provides low line frequency harmonics but requires high switching or a large inductor to provide low current ripple since only bi- level control is available. Modification of the ZACE concept is required to handle multi-level inverters. A new ZACE method is proposed that can handle the voltage transition in a single-phase multi-level inverter. Simulation results are presented for a grid-
connected single-phase five-level inverter to demonstrate the concept. The pulse width modulation (PWM) inverter functions around the concept of placing discrete voltages across a filtering inductor and load as shown in Fig. I. The inductor integrates the voltage waveform to produce a current. By varying the polarity and amplitude of the applied voltage, sinusoidal current waveforms can be created. The output current waveform, because it
is the integral of the applied voltage, contains ripple. It is desirable to limit the amplitude of the current ripple with respect to the amplitude of the current waveform. The magnitude of the ripple is a function of inductor size, switching frequency and the number of discrete input voltage levels.
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